1. Field of the Invention
The present invention relates to the packaging of electronic components such as integrated circuits or other electronic devices. In particular, this invention relates to a stacked semiconductor device package wherein a substrate of the stacked semiconductor package is smaller than at least one semiconductor device of the stacked semiconductor package.
2. State of the Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices connected thereto, various types of increased density packages have been developed. Among these various types of packages is the so-called “multi-chip module” (MCM). Some types of multi-chip modules include assemblies of semiconductor devices that are stacked one on top of another. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent; a stack of semiconductor devices consumes roughly the same amount of real estate on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Due to the disparity in processes that are used to form different types of semiconductor devices (e.g., the number and order of various process steps), the incorporation of different types of functionality into a single semiconductor device has proven very difficult to actually reduce to practice. Even in cases where semiconductor devices that carry out multiple functions can be fabricated, multi-chip modules that include semiconductor devices with differing functions (e.g., memory, processing capabilities, etc.) are often much more desirable since the separate semiconductor devices may be fabricated independently and later assembled with one another much more quickly and cost-effectively (e.g., lower production costs due to higher volumes and lower failure rates).
Multi-chip modules may also contain a number of semiconductor devices that perform the same function, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
An example of a conventional, stacked multi-chip module includes a carrier substrate, a first, larger semiconductor device secured to the even larger carrier substrate, and a second, smaller semiconductor device positioned over and secured to the first semiconductor device. The second, smaller semiconductor device does not overlie bond pads of the first semiconductor device and, thus, the second semiconductor device does not cover bond wires that electrically connect bond pads of the first semiconductor device to corresponding contacts or terminals of the carrier substrate. Thus, the carrier substrate must be even larger than the first, larger semiconductor device for electrical connection thereto. Such a multi-chip module is disclosed and illustrated in U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter “the '767 Patent”). Notably, since sizes of the semiconductor devices of such a multi-chip module must continue to decrease as they are positioned increasingly higher on the stack, the obtainable heights of such multi-chip-modules become severely limited.
Another example of a conventional multi-chip module is described in U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994 (hereinafter “the '060 Patent”). The multi-chip module of the '060 Patent includes a carrier substrate with semiconductor devices disposed thereon in a Chip-On-Board (“COB”) stacked arrangement. The individual semiconductor devices of each multi-chip module may be the same size or different sizes, with upper semiconductor devices being either smaller or larger than underlying semiconductor devices. Adjacent semiconductor devices of each of the multi-chip modules disclosed in the '060 Patent are secured to one another with an adhesive layer. The thickness of each adhesive layer well exceeds the loop heights of wire bonds protruding from a semiconductor device upon which that adhesive layer is to be positioned. Accordingly, the presence of each adhesive layer prevents the back side of an overlying, upper semiconductor device from contacting bond wires that protrude from an immediately underlying, lower semiconductor device of the multi-chip module. The carrier substrate is larger than the semiconductor devices, and the bond wires are bonded to the carrier substrate on regions peripheral to the stacked semiconductor devices. It does not appear that the inventors named on the '060 Patent were concerned with the size of the carrier substrate or the length of the bond wires. Thus, the multi-chip modules of the '060 Patent may have an undesirably large foot print and undesirably long bond wires due to the peripheral wire bond connections. A multi-chip module having a large foot print may restrict the routing space for external circuitry, for example a printed circuit board. Long bond wires result in more potential for interwire contact and shorting, and more inductance.
Other suitable techniques used for bonding and electrically connecting a semiconductor device to a substrate are flip-chip attachment and Board-On-Chip (“BOC”) assembly.
Flip-chip attachment generally consists of attaching an active surface of a semiconductor device to a substrate with a plurality of conductive bumps therebetween. Each conductive bump must align and correspond with respective bond pads on the substrate and the semiconductor device to provide electrical interconnection therebetween. The semiconductor device is bonded to the substrate by reflowing the conductive bumps, after which an underfill material is typically disposed between the semiconductor device and the substrate for environmental protection and to enhance the attachment of the semiconductor device to the substrate.
Turning to the BOC assembly, the semiconductor device may be attached to the surface of a substrate in a face down orientation (with its active surface and bond pads down with respect to the circuit board). In this orientation, the active surface of the device is adhesively attached to a portion of the substrate having one or more wire bonding openings therein, so that bond wires can extend through the opening from bond pads on the substrate to bond pads on the active surface of the device. A bond wire is then discretely attached to each bond pad on the semiconductor device and extends to a corresponding bond pad on the substrate. The bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding, using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding, using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. An encapsulant is typically used to cover the bond wires to prevent contamination. For an exemplary BOC assembly, see U.S. Pat. No. 5,719,440, issued to Moden on Feb. 17, 1998, and assigned to the assignee of the present invention, which discloses the device adhesively attached face (active surface) down to a substrate with wire bonding through an opening in the substrate.
This face down semiconductor device orientation is advantageous by allowing shorter wire bonds. However, a conventional multi-chip module having a first semiconductor device on a substrate in a BOC assembly includes a second semiconductor device stacked thereover and a carrier substrate larger than both the first semiconductor device and the second semiconductor device. Bond wires electrically connecting the second semiconductor device and the carrier substrate are bonded to the carrier substrate on regions peripheral to the stacked semiconductor devices. For example, see U.S. Pat. No. 6,472,736 issued to Yeh et al. on Oct. 29, 2002.
In view of the foregoing, it appears that a method for forming stacked semiconductor device assemblies which enables the use of shorter bond wires and a substrate smaller relative to the semiconductor devices would be useful.